1. Field of the Invention
The present invention relates to a semiconductor chip inspection supporting apparatus for supporting a semiconductor chip inspection.
2. Description of the Related Art
In a semiconductor manufacturing process, a plurality of semiconductor chips (hereinafter referred to as “chips”), each of which includes circuit elements, is formed on a semiconductor wafer so as to build circuits thereon. The plurality of chips is inspected (measured) with a probe card and a measuring instrument for examination of electrical characteristics. Those chips judged as good through the inspection are shipped.
During the chip inspection, simultaneous measurements of multiple chips are performed in order to reduce the inspection time. In the simultaneous measurements of multiple chips, the number of chips to be measured simultaneously can be increased by performing paired measurement in which a measuring pin is shared between two chips. However, since the shape of a chip is typically quadrangular while the shape of a semiconductor wafer is generally a circular, a plurality of normal chips and a plurality of abnormal chips are formed on the semiconductor wafer. Here, the normal chip is a chip that builds a circuit on the semiconductor wafer. The abnormal chip is a chip that cannot build a circuit on the semiconductor wafer. The abnormal chip is formed, for example, near an end portion of the semiconductor wafer. This abnormal chip is separated from the semiconductor wafer to be used as one device in a later step.
In the paired measurement, with the probe card (probe) being set on the normal chip and the abnormal chip, a voltage may be applied from the measuring instrument in some cases. In this case, a current leakage occurs. This leakage causes a phenomenon such as a leakage trouble or voltage decrease in the measuring pin. This results in malfunction of the normal chips. Therefore, the following methods have been adopted in conventional practices:
(Method 1) Measurement time reduction based on simultaneous measurements of multiple chips is prioritized. Thus, the occurrence of malfunctions of some normal chips is abandoned;
(Method 2) Considerable manpower (including labor cost) and time are dedicated to determining chip combinations;
(Method 3) Simultaneous measurements of multiple chips are abandoned to eliminate the malfunction of some normal chips; and
(Method 4) Considerable manpower (including labor cost) is dedicated to taking countermeasures (disconnection between the Pad and the inside) against abnormal chips so as to achieve simultaneous measurement of multiple chips.
In conjunction with the chip inspection, the conventional techniques are disclosed as shown below.
Japanese Laid-Open Patent Application JP-A-Heisei, 04-133443 discloses a method for manufacturing a semiconductor device, which relates to a case where a plurality of chips are simultaneously measured in a wafer probing test. In order to enable the probing test to be performed easily, this manufacturing method prevents the probe of a probe card from selecting a section other than chips laid on the wafer.
Japanese Laid-Open Patent Application JP-A-Heisei, 06-168991 discloses a multi-probing semiconductor inspection method, which enables an inspection of a semiconductor chip with high inspection efficiency without causing an increase in the transfer range of a wafer transfer device.
Japanese Laid-Open Patent Application JP-A-Heisei, 09-270446 discloses a semiconductor inspection device, which is capable of inspecting a semiconductor device in which a plurality of product chips and one TEG chip are formed with the same shot.
Japanese Laid-Open Patent Application JP-P2004-55910A discloses a probe device, which is easily adaptable to a change in the layout of a probe card or the arrangement of an identification number.
Japanese Laid-Open Patent Application JP-P2000-40720A discloses an IC test system, which is capable of reading even location data to be specified at later time and also which operates by using new location data that permits reading the probe layout without a conversion table for each location data being provided to an IC test device.
Japanese Laid-Open Patent Application JP-A-Heisei, 10-160798 discloses an IC test method, which is capable of efficiently performing a test with a shorter measurement time even when only one measurement condition is provided at a time during simultaneous measurement of a plurality of ICs.
Japanese Patent JP-P3107798B discloses a semiconductor device inspection apparatus, which is capable of easily managing probe card usage history data at low costs.
Japanese Laid-Open Patent Application JP-A-Heisei, 07-169800 discloses a method of determining a probe card regular inspection period, which automatically judges a regular inspection period to be performed for a probe card that is used in semiconductor manufacturing, based on the time elapsed and the number of usage after the last regular inspection of the probe card, and then notifying the operator of this period.
Japanese Laid-Open Patent Application JP-P2001-230181 discloses a shot map creation method, which is capable of providing an improved throughput.